Current techniques to cool semiconductor ICs (integrated circuits) use chip packages with externally mounted, finned heat sinks coupled to the ceramic or plastic encapsulated IC chip. As the speed and density of modern ICs increase, the power generated by these chips also increases, often in geometric proportion to increasing density and functionality. In the video processing and CPU (central processing unit) application areas, the ability to dissipate the heat being generated by current ICs is becoming a serious limitation in the advance of technology. While some aspects of the problem can be mitigated by forced convection devices such as fans (and even liquid cooling), the core of the problem is now shifting to the thermal resistances within the chip itself. Reducing the outer package surface temperature is producing diminishing returns due to the high heat fluxes being generated at the semiconductor junctions, and the relatively poor thermal conductivity of the materials between the junction and the outer package surface. This problem is producing high junction temperatures that directly affect chip reliabilities. Other than the available chip design techniques used to minimize IC power generation (e.g., lowering voltage, clocking schemes to turn-off transistors when inactive, and decreasing the size of specific, non-critical transistors), the current art does not provide efficient solid structures inside the chip to carry heat out and reduce junction temperatures.
Heat generated near or at the silicon active devices (semiconductor junctions) is dissipated through two paths:
(a) through the inter-metal dielectrics and metal layers to the top bonding layer, or
(b) through the bulk silicon towards the bottom of the wafer where thermal contact is made to the back of the chip with the package's heat sink.
Both paths have high thermal resistance. In the current art, the limiting factors are the ‘insulator’ thermal characteristics of dielectrics and bulk silicon materials. More limiting yet is the fact that the path to heat conduction is usually at the bottom or back of the chip through the bulky silicon substrate. As the number of metal and insulator layers grows to accommodate chip interconnect, an increase of their temperature is anticipated. With heat sinking only at one side of the chip it becomes harder to ‘cool’ the chip. As a result, large and fast-switching transistors can have their individual junction temperature rise above certain maximum values. This is also true for metal wires with high current and switching activity.